PIC16F627-04/P【PDF 89/170 页】IC MCU FLASH 1KX14 COMP 18DIP

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Sheet目录3873

85页 86页 87页 88页 [89页]90页 91页 92页 93页

2003 Microchip Technology Inc.

Preliminary

DS40300C-page 23

PIC16F62X

3.2.2.5

PIR1 Register

This register contains interrupt flag bits.

PIR1 REGISTER (ADDRESS: 0Ch)

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable

bit,

GIE

(INTCON<7>).

User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0

R-0

U-0

R/W-0

EEIF

CMIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

bit 7

EEIF: EEPROM Write Operation Interrupt Flag bit

= The write operation completed (must be cleared in software)

= The write operation has not completed or has not been started

bit 6

CMIF: Comparator Interrupt Flag bit

= Comparator output has changed

= Comparator output has not changed

bit 5

RCIF: USART Receive Interrupt Flag bit

= The USART receive buffer is full

= The USART receive buffer is empty

bit 4

TXIF: USART Transmit Interrupt Flag bit

= The USART transmit buffer is empty

= The USART transmit buffer is full

bit 3

Unimplemented: Read as ‘0’

bit 2

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare Mode

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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